A. Field of the Invention
The present invention relates to a semiconductor device having a trimming circuit.
B. Description of the Related Art
In a semiconductor integrated circuit, adjustment is carried out using a method known as trimming in order to correct fluctuation in circuit characteristics caused by manufacturing variation. A fuse resistor, Zener zap diode, or the like, is used as a trimming element.
A fuse resistor is normally a polysilicon resistor formed of a polysilicon film, wherein a short circuit state between terminals of the fuse resistor is changed to an open circuit state by the polysilicon resistor being fused. As methods of fusing the fuse resistor, there is a method using a laser, and a method whereby current is caused to flow and the Joule heat of the current utilized. The method whereby current is caused to flow is widely used, as it can be comparatively simply implemented utilizing an external voltage source or a voltage source incorporated in an integrated circuit.
A Zener zap diode causes short circuit breakdown with an avalanche current in a p-n junction by applying a voltage, thus causing a change from an open circuit state to a short circuit state between a cathode terminal and an anode terminal.
A trimming circuit is configured of the trimming element alone, or of a circuit including the trimming element, and the circuit characteristics of a semiconductor integrated circuit are corrected by bringing about a short circuit state or open circuit state between a first terminal and second terminal, which are output terminals of the trimming circuit, thereby changing the circuit constants.
FIGS. 12(a) and 12(b) are circuit diagrams showing cases in which series resistor circuit 50 is adjusted using trimming circuits 51 and 52, wherein FIG. 12(a) is a diagram of a case in which fuse resistor 53 is used as trimming circuit 51, and FIG. 12(b) is a diagram of a case in which Zener zap diode 54 is used as trimming circuit 52.
In FIG. 12(a), one end of series resistor circuit 50, which is configured of five resistors R1 to R5, is connected to power supply terminal 61, the other end is connected to a ground GND, and a reference voltage VREF is output from reference voltage terminal 62 connected to a connection point of the uppermost stage resistor R1 and second stage resistor R2. First terminal 53a and second terminal 53b of fuse resistor 53 are connected with two ends of the lowermost stage resistor R5, respectively. The design is such that when a power supply voltage VDD0 is applied to power supply terminal 61, the reference voltage VREF=V1 is output. When the manufacturing process is finished, VDD0 is applied to power supply terminal 61, the reference voltage VREF is measured, and a voltage lower than V1 is indicated due to manufacturing variation, fuse resistor 53 of trimming circuit 51 is fused. By fuse resistor 53 being fused, there is a change to an open circuit state between first terminal 53a and second terminal 53b, and the reference voltage VREF increases. By VREF increasing, VREF nears V1, which is the set voltage, and is thus adjusted.
In FIG. 12(b), one end of series resistor circuit 50 configured of the five resistors R1 to R5 is connected to power supply terminal 61, the other end is connected to the ground GND, and the reference voltage VREF is output from the reference voltage terminal 62 connected to the connection point of the uppermost stage resistor R1 and second stage resistor R2. First terminal 54a and second terminal 54b of Zener zap diode 54 of trimming circuit 52 are connected with two ends of the lowermost stage resistor R5, respectively. The design is such that when the power supply voltage VDD0 is applied to power supply terminal 61, the reference voltage VERF=V1 is output. When the manufacturing process is finished, VDD0 is applied to power supply terminal 61, the reference voltage VREF is measured, and a voltage higher than V1 is indicated due to manufacturing variation, Zener zap diode 54 of trimming circuit 52 is short circuited. By Zener zap diode 54 being short circuited, there is a change to a short circuit state between first terminal 54a and second terminal 54b, and the reference voltage VREF decreases. By VREF decreasing, VREF nears V1, which is the set voltage, and is thus adjusted.
Trimming is also possible in the same way when using a series MOSFET circuit, wherein MOSFETs are connected in series, instead of series resistor circuit 50. In this case, it is good when the first terminal and second terminal of the trimming circuit are connected to the drain and source of a MOSFET.
In JP-A-2003-110029, a description is given of a semiconductor device and trimming method thereof such that an increase in IC chip area and external terminals is suppressed, and no retrimming is carried out after the final trimming adjustment is finished.
In Japanese Patent No. 2,944,573, a description is given of a semiconductor integrated circuit such that it is possible before trimming to confirm the operating state after trimming, without providing a dedicated circuit or an extra data input pad for confirming trimming in advance.
Examples of a trimming circuit using a polysilicon fuse are shown in JP-A-2003-110029 and Japanese Patent No. 2,944,573.
In JP-A-2008-192986, a description is given of fuse elements being deposited in an upper portion of a resistor. Furthermore, a description is given of a semiconductor device and manufacturing method thereof such that, by a depressed form being adopted for a resistor below a region of the fuse element cut off by laser, the resistor is of a small area and suffers little damage when cutting off the fuse element, contact resistance and the like occurring between elements is low, and stability is provided.
In JP-A-2002-100761, a polysilicon lateral diode is formed and connected between a high frequency input/output signal line and an external supply power supply VDD, and between an external ground voltage GND and the high frequency input/output signal line, so that each of an orientation from the high frequency input/output signal line to the external supply power supply VDD and an orientation from the external ground voltage GND to the high frequency input/output signal line is the diode forward direction. It is described that, because of this, it is possible to provide a highly reliable, sophisticated high frequency Si-MOS semiconductor device having high ESD resistance.
In JP-A-2001-320019, a configuration includes a p-type thin film resistor formed of a p-type semiconductor thin film and an n-type thin film resistor formed of an n-type semiconductor thin film, wherein a change in the resistance value when stress is exerted is compensated for. A manufacturing method whereby this is obtained is such that a low resistance region is formed simultaneously inside an n-type polycrystalline silicon resistor in the step of forming the source and drain of an NMOS transistor. It is described that by a low resistance region being formed simultaneously inside a p-type polycrystalline silicon resistor in the step of forming the source and drain of a PMOS transistor region, it is possible to provide a semiconductor device having a bleeder resistor circuit wherein the resistance value does not fluctuate in response to stress.
In JP-A-2000-133778, it is described that a trimming circuit using a fuse of an LCD controller IC having a plurality of gate oxide films is such that, by using an oxide film other than the thinnest oxide film for the gate oxide film of an input circuit transistor, and using an oxide film other than the thinnest of the plurality of oxide films for the input circuit transistor, breakdown of the input circuit gate oxide film when fuse trimming is prevented, and characteristics are not caused to deteriorate even by an application of voltage when fuse trimming.
In JP-A-2006-294903, a description is given of a method of preventing a fuse resistor being cut off by an application of static electricity to a trimming pad.
In JP-A-2013-7619, it is described that, by adopting a logic circuit and voltage detector circuit including a first fuse connected between a power supply terminal and output terminal and a second fuse connected between a ground terminal and output terminal, and including a logic selection circuit such that either the first fuse or second fuse is necessarily cut off when selecting output logic, current consumption is suppressed regardless of whether a high level or low level output logic is selected.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.